EPICS IOC exposes all configuration parameters, statuses and measurement data as EPICS Process Variables (PVs). It consists of three main parts: FPGA Control, exposes application specific configuration particular to the FPGA, Comm. Board control exposes the parameters of the Comm. Board (slow data), and the Measurement Data Handling exposes the measurement data (fast data). Additionally the Measurement Data Handling also sends the measurement data to the Beam Synchronous Data Acquisition Dispatching Layer by using already prepared EPICS driver for this purpose (epics_bsread).
Measurement data handling takes the following course for every pulse of the machine (Figure 5): Unique Pulse ID is delivered from the Timing System to the FPGA for each pulse. The Pulse ID is received by the Embedded Event Receiver on the IFC1210 FPGA and transmitted as DELFI Event Data to the Comm. Board. The Comm. Board acquires data and adds the Pulse ID in the header of the data frame when sending it over DELFI link back to the FPGA. This way the data is reliably tagged with correct pulse ID. EPICS IOC exposes all the data over Channel Access (CA) protocol and also streams the data to the Beam Synchronous Data Acquisition Dispatching Layer.
Figure 5: Sequence diagram of one machine pulse
A graphical user interface was developed in CaQtDm  which provides a full control over all parts of the application from configuring the analog frontends through changing data acquisition parameters on the Comm. Board to configuring the embedded EVR.
The application was first designed to handle 15 DELFI links and one Event Timing Link on one IFC1210. At this point it was not yet clear whether the calibration procedure will run on the IFC1210 or will it be done off-line. Once the calibration was implemented on the IFC1210 it turned out that the processor can not process that amount of measurement data in the available time. The number of links per IFC1210 was reduced. Currently all installations are using only one DELFI link per IFC1210.
The majority of the EPICS IOC was written in EPICS database files which became difficult to maintain. In some cases it was also limiting the functionality. Parts of the the application had to be rewritten later to C.
It was observed that the data delivered to the Beam Synchronous Data Acquisition Dispatching Layer was not always consistent. Tests are being developed to confirm the inconsistency and at the same time parts of the application are being improved to address this issue.
DELFI protocol was developed to allow deterministic triggering and data acquisition over the same full duplex serial interface. It was integrated into the SwissFEL environment and proven to work in practice. It is already planned to be used in other facilities at Paul Scherrer Institute.
 C.Milne, et al.,“SwissFEL: The Swiss X-Ray Free-Electron Laser”, inApplied Sciences (Switzerland), vol. 7, no. 7, article 720, Jun. 2018
 Kalantari and R. Biffiger, “SwissFEL Timing System: First Operational Experience”, inProc. 16th Int. Conf. on Accelerator and Large Experimental Control Systems (ICALEPCS’17), Barcelona, Spain, Oct. 2017, pp. 232-237. doi:10.18429/JACoW-ICALEPCS2017-TUCPL04
 G. Ebner et al., “SwissFEL – Beam Synchronous Data Acquisition – The First Year”, inProc. 16th Int. Conf. on Accelerator and Large Experimental Control Systems (ICALEPCS’17), Barcelona, Spain, Oct. 2017, pp. 276-279. doi:10.18429/JACoW-ICALEPCS2017-TUCPA06
 A. Franaszek and A. X. Widmer,“A DC-Balanced, Partitioned-Block, 8B/10B Transmission Code” inIBM Journal of research and development, vol. 27, no. 5.,1983
 Kalantari, R. Biffiger, S. Skube, T. Slejko, T. Šuštar, “SwissFEL Event Timing System”, poster atAnnual meeting of the Swiss Physical Society, Lausanne, Switzerland, 2018.
 IOxOS Technologies AS, “IFC_1210 – Intelligent FPGA Controller P2020 VME64x Single Board Computer”, Data Sheet, 2011
 IOxOS Technologies AS, “TOSCA II Xilinx Virtex-6T FPGA Design Kit”, Data Sheet, 2010
 IOxOS Technologies AS, “EPICS Driver for TOSCA II Infrastructure IFC_1210”, Data Sheet, 2013